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Improving Energy Efficiency in Multi-processor Soft-Core Systems Using System-level Techniques

Biglari, Mehrdad | 2015

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 47051 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Goudarzi, Maziar
  7. Abstract:
  8. The ever increasing density and performance of FPGAs, has increased the importance and popularity of soft processors. One major research concern in this regard lays in the field of energy efficiency of the system on FPGA. This work is particularly focused on the energy efficiency of multiprocessor structures on FPGA using system level techniques. The growing gap between the speed of processors and memories can partly be compensated through memory hierarchy, i.e. caches. Since memory accesses follow a non-uniform distribution, and vary from one application to another, variable set-associative cache architectures have emerged. In this thesis, two novel cache architecture, primarily aimed at soft processors, for single processor and multi processor platforms based on FPGA are proposed to address the variable access demands of applications, through dynamically configurable line-associativity, with no memory overhead. In the proposed single processor structure, this improvement is achieved by using victim blocks with fine grained configuration. In the proposed multi processor structure, this improvement is realized by utilization of unused blocks of each processor's cache by other processors. The proposed architectures reduce the miss count and improve the instruction per cycle (IPC) of the system compared to a system with a direct map cache. Reduction in the miss count directly translates into lower power consumption, since it introduces less off-chip memory references. The reduction in power consumption of the system and the execution type of it results in a considerable reduction in energy consumption of the system
  9. Keywords:
  10. Multiprocessor System ; Field Programmable Gate Array (FPGA) ; Energy Efficiency ; System Level Optimization ; Optimization ; Soft Processor

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