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A novel low power architecture for DLL-based frequency synthesizers

Gholami, M ; Sharif University of Technology | 2013

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  1. Type of Document: Article
  2. DOI: 10.1007/s00034-012-9488-9
  3. Publisher: 2013
  4. Abstract:
  5. This paper presents a novel DLL-based frequency synthesizer architecture to generate fractional multiples of reference frequency and reduce the power consumption of the frequency synthesis block. The architecture is adopted for French VHF application as an example. The DLL architecture allows for minimal area, while consuming low power. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. It was shown that for the mentioned standard, a mere 27 delay stages for VCDL are sufficient to cover French VHF band. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is implemented in a 0.13 μm CMOS technology. This fractional DLL-based frequency synthesizer is adopted for 176 MHz to 216 MHz with maximum power consumption of 2.62 mW and RMS jitter of 10 ps @ 216 MHz
  6. Keywords:
  7. Fractional multiple ; Low supply voltages ; Frequency synthesizer ; Analytical predictions ; Delay-locked loops ; Frequency synthesis ; Low power architecture ; Delay Locked Loop ; Synthesizer architecture ; System level design ; CMOS integrated circuits ; Jitter ; Phase noise ; Frequency synthesizers
  8. Source: Circuits, Systems, and Signal Processing ; Volume 32, Issue 2 , 2013 , Pages 781-801 ; 0278081X (ISSN)
  9. URL: http://link.springer.com/article/10.1007%2Fs00034-012-9488-9