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A low-latency low-power QR-decomposition ASIC implementation in 0.13 μm CMOS

Shabany, M ; Sharif University of Technology | 2013

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSI.2012.2215775
  3. Publisher: 2013
  4. Abstract:
  5. This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm 2 QRD chip, fabricated in 0.13 μm 1P8M CMOS technology, demonstrate that the proposed design for 4×4 complex matrices attains the lowest reported processing latency of 40 clock cycles (144 ns) at 278 MHz and dissipates 48.2 mW at 1.3 V supply and 25° C. It outperforms all of the previously published QRD designs by offering the highest QR processing efficiency
  6. Keywords:
  7. MIMO ; Innovative design ; QRD decomposition ; very large scale integration ; Clock cycles ; CMOS technology ; Complex matrices ; CORDIC processors ; Gate count ; Givens Rotation ; Householder transformation ; Application specific integrated circuits ; Low Power ; Low-latency ; Number of cycles ; QR decomposition ; Resource utilizations ; Rotation operations ; CMOS integrated circuits ; MIMO systems ; Signal receivers ; VLSI circuits ; Design
  8. Source: IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 60, Issue 2 , 2013 , Pages 327-340 ; 15498328 (ISSN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6419866