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Using partial tag comparison in low-power snoop-based chip multiprocessors

Shafiee, A ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1007/978-3-642-24322-6_18
  3. Abstract:
  4. In this work we introduce power optimizations relying on partial tag comparison (PTC) in snoop-based chip multiprocessors. Our optimizations rely on the observation that detecting tag mismatches in a snoop-based chip multiprocessor does not require aggressively processing the entire tag. In fact, a high percentage of cache mismatches could be detected by utilizing a small subset but highly informative portion of the tag bits. Based on this, we introduce a source-based snoop filtering mechanism referred to as S-PTC. In S-PTC possible remote tag mismatches are detected prior to sending the request. We reduce power as S-PTC prevents sending unnecessary snoops and avoids unessential tag lookups at the end-points. Furthermore, S-PTC improves performance as a result of early cache miss detection. S-PTC improves average performance from 2.9% to 3.5% for different configurations and for the SPLASH-2 benchmarks used in this study. Our solutions reduce snoop request bandwidth from 78.5% to 81.9% and average tag array dynamic power by about 52%
  5. Keywords:
  6. Cache Miss ; Chip Multiprocessor ; End-points ; Lookups ; Low Power ; Partial tag ; Power Optimization ; Snoop filtering ; Snoop-based cache coherency ; Tag arrays ; Benchmarking ; Computer architecture ; Optimization ; Systems analysis ; Microprocessor chips
  7. Source: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 19 June 2010 through 23 June 2010 ; Volume 6161 LNCS , June , 2012 , Pages 211-221 ; 03029743 (ISSN) ; 9783642243219 (ISBN)
  8. URL: http://link.springer.com/chapter/10.1007%2F978-3-642-24322-6_18