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A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults

Jabbarvand Behrouz, R ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/ICCD.2011.6081436
  3. Abstract:
  4. As the semiconductor industry advances to the deep sub-micron and nano technology points, the on-chip components are more prone to the defects during manufacturing and faults during system operation. Consequently, fault tolerant techniques are essential to improve the yield of modern complex chips. We propose a fault-tolerant routing algorithm that keeps the negative effect of faulty components on the NoC power and performance as low as possible. Targeting intermittent faults, we achieve fault tolerance by employing a simple and fast mechanism composed of two processes: NoC monitoring and route adaption. Experimental results show the effectiveness of the proposed technique, in that it offers lower average message latency and power consumption and a higher reliability, compared to some related work
  5. Keywords:
  6. Fault-tolerant routing ; Intermittent faults ; Latency ; NoC ; Permanent faults ; Fault tolerant routing ; Intermittent fault ; Algorithms ; Electric fault currents ; Manufacture ; Network architecture ; Routing algorithms ; Semiconductor device manufacture ; VLSI circuits ; Fault tolerance
  7. Source: Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors ; 2011 , Pages 433-434 ; 10636404 (ISSN) ; 9781457719523 (ISBN)
  8. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6081436