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Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors

Fazeli, M ; Sharif University of Technology | 2011

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  1. Type of Document: Article
  2. DOI: 10.1016/j.microrel.2011.06.008
  3. Publisher: 2011
  4. Abstract:
  5. This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the embedded processors. To exploit the first fact for fault tolerance purpose, the unused parts of a particular arithmetic or logic circuit can be used to provide redundant computations. The second fact also offers us assisting the other unused arithmetic circuits of the ALU to provide redundant computation while a particular arithmetic circuit is being used to perform a specific operation. In this paper, we have implemented a 32-bit ALU protected by the OWHR technique using VHDL and we have extracted the results of power and performance overheads using Synopsis Design and Power Compiler. To do this, we have profiled the input operands of the adder and multiplier units by running some programs of MiBench embedded suite benchmark on an ARM processor performance mode. We have then applied the profiled operands to the implemented ALU to extract the power and performance overheads. The simulation results show that the proposed technique is capable of correcting about 56% of errors in the adder circuit and about 88% of errors in multiplier circuit while having the ability of detecting 100% of errors in the both of the circuits. Beside its high level of reliability, it offers the benefits of low power, and area overheads
  6. Keywords:
  7. Adder circuit ; Area overhead ; Arithmetic circuit ; ARM processor ; Embedded processors ; Fault-tolerant ; Hardware reuse ; Low costs ; Low Power ; Most significant bit ; Multiplier circuits ; Narrow width ; Redundant computation ; Adders ; Benchmarking ; Design ; Errors ; Integrating circuits ; Multiplying circuits ; Logic circuits
  8. Source: Microelectronics Reliability ; Volume 51, Issue 12 , December , 2011 , Pages 2374-2387 ; 00262714 (ISSN)
  9. URL: http://www.sciencedirect.com/science/article/pii/S0026271411001983