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System Level Modeling and Optimization of Accelerator-CPU Communication in Data Centers

Haji Ali Khamseh, Amir | 2015

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 48184 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Goudarzi, Maziar
  7. Abstract:
  8. Due to the data centers rapid growth and introduction of a new basic type of massive data processing platforms which requires accelerators to speedup computation and enhance the efficiency and reduce power consumption, using accelerators is inevitable. Communication and data transfer time between software and hardware is the most of time spent on the use of accelerators. By optimizing this part of the hardware / software platform, we have achieved substantial results in this area. The aim of our study is to organize a survey of real accelerator characteristics. To figure out its defects and main drawbacks, in addition to improving the overall efficiency of system. The implementation of accelerator alongside the central processor requires system change and update in available hardware and software, however; by exploiting both concurrent processing and data transmission in appropriate time schedules, increasing efficiency is feasible.In order to speed-up an application, slow regions are detected by the proposed heuristic algorithm after basic analysis and adaption to proposed model. Selected regions are organized by analyzing critical path to maximize the processing and data transmission concurrency during application run time
  9. Keywords:
  10. Accelerators ; Hardware-Software Co-Design ; Concurrency ; Field Programmable Gate Array (FPGA) ; Speedup Analysis ; Data Center

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