Loading...

Accelerating Perfect and Imperfect Loops Using Reconfigurable Architectures

Tanhaee, Effat | 2015

473 Viewed
  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 48769 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hesabi, Shahin
  7. Abstract:
  8. With the widespread use of mobile applications, multimedia and telecommunications, speed of execution has become important. The computation-intensive portions of applications, i.e., loops, devote a significant percentage of their implementation time. Thus, in this thesis, a new method is introduced which greatly increases the execution speed of the loops. Loops are often implemented on coarse-grained reconfiguration architecture (CGRAs) for acceleration, which is a promising architecture with high performance and high power efficiency in comparison to FPGA. In this regard, to reduce the execution time of two-level nested loops, if there are several innermost loops, first, we fuse them, then the outermost and innermost loop trip count will be sent to CGRA. After that, if it is possible, the outermost or the innermost loop trip count will break. According to our approach, the main loop is divided into several sub-loops, and they run simultaneously. Thus nested loop execution time is reduced. By employing the presented method, we have gained 99% improvement on speed of implementation of the loops on coarse-grained reconfiguration architecture with 16 processing element, in comparison to Micro-blaze. Also, the performance in the best case and worst case has been improved by 45% and 30%, respectively in comparison to the new technologies, while the increase of the power consumption is negligible
  9. Keywords:
  10. Coarse Grained Model ; Reconfigurable Architecture ; Acceleration ; Loops ; Imperfect Loops ; Perfect Loops ; Sub-Loop ; Processing Element

 Digital Object List

 Bookmark

No TOC