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Modeling of DLL-based frequency multiplier in time and frequency domain with Matlab Simulink

Gholami, M ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/APCCAS.2010.5775021
  3. Abstract:
  4. A systematic procedure of simulating charge pump based delay locked loops (DLLs) represents in this paper. The presented procedure is based on the systematic modeling of the DLL components in Matlab Simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented
  5. Keywords:
  6. Delay locked loop ; DLL ; DLL modeling ; Frequency synthesizer modeling ; MATLAB simulink ; Charge pump ; Clock signal ; Delay-locked loops ; Design considerations ; DLL ; Frequency multiplier ; Input frequency ; Simulation result ; Systematic modeling ; Time and frequency domains ; Whole systems ; Charge pump circuits ; Frequency multiplying circuits ; Frequency synthesizers ; Multiplying circuits ; MATLAB
  7. Source: IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 6 December 2010 through 9 December 2010 ; 2010 , Pages 1051-1054 ; 9781424474561 (ISBN)
  8. URL: http://ieeexplore.ieee.org/document/5775021