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Performance Evaluation of Physical Unclonable Functions and Proposing a Scheme on FPGA
Ramezani, Alireza | 2016
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- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 48728 (19)
- University: Sharif University of Technology
- Department: Computer Engineering
- Advisor(s): Bayat-Sarmadi, Siavash
- Abstract:
- In recent years, in addition to traditional cryptographic blocks, a hardware blocks in this work namely PUF, has been used mostly for chip ID generation, authentication and so on. In this work we study recent proposed PUFs and their implementations on FPGA, and the measurement of quality metrics on them. Some of most important characteristics of PUFs are unpredictability, reliability, number of challenge response pairs and area. According to experiments that have been performed in this study and also according to previous work, one high-quality PUF in term of uniqueness and reliability is Ring Oscillator PUF. However, the disadvantage of this PUF is small number of challenge and response pairs. Proposed ideas in some of these papers increase area of RO PUFs. Small number of challenge and response pairs, large area consumption by RO PUF makes it inefficient for numerous applications. In this study an architecture based on RO PUF on an FPGA platform has been proposed. The proposed architecture increases the challenge response pairs, and also reduces the RO PUF area and prevents it from exponential growth of area rather than increase in challenge and response in RO PUF. In this study, 42747 challenge response pairs can be obtained from the proposed PUF while implementation of RO PUF with same number of challenge response pairs requires 85494 rings. The number of configuration bits to generate a response bit in proposed architecture is twelve times of the number of switches, which is larger than that for RO PUF
- Keywords:
- Performance Evaluation ; Reconfigurable Devices ; Field Programmable Gate Array (FPGA) ; Challeng Response Pairs Enhancement ; Physical Unclonable Function (PUF)
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