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An Efficient Reconfigurable Architecture in Embedded Processors

Tamimi, Sajjad | 2016

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 48833 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Asadi, Hossein
  7. Abstract:
  8. Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, Field-Programmable Gate Arrays (FPGAs) are used in industry for implementing either an entire embedded system or a Hardware Description Language (HDL)-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors. In this thesis, we present an efficient reconfigurable architecture to implement embedded processors in SRAM-based FPGAs by exploiting characteristics such as low utilization and continues accessibility of comprising components. To this end, we integrate the low-utilization computational components into a single reconfigurable unit. The proposed reconfigurable unit is made up of a set of Standard Cells (SCs) and/or Configurable Hard Logics (CHLs) to implement identical or similar logic functions of low-utilization components, and typical Look-Up Tables (LUTs) for the other parts. We have evaluated the effectiveness of the proposed architecture by implementing the Berkeley RISCV processor and running MiBench benchmarks. We have also examined the applicability of the proposed architecture on an alternative open-source processor (LEON2). Experimental results show that the proposed architecture as compared to the conventional FPGAs improves the area efficiency and static power consumption by 58.6% and 58.4%, respectively. In addition, while the average critical path delay of computational units is improved by 8.4%, the overall run-time of applications is increased by 30.2%, on average, due to the imposed inter-component reconfiguration overhead
  9. Keywords:
  10. Field Programmable Gate Array (FPGA) ; Embedded Processor ; Reconfigurable Architecture ; Reconfigurable Hard Logic

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