An Optimized Automated Design Algorithm for Pipeline ADC

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Sadrafshari, Mir Vala | 2016

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 48823 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Sharifkhani, Mohammad
Abstract:
Analog to digital converters with different specifications are widely used in modern electronic circuits. The significant demand on pipeline converters in several low power applications is mainly due to their high speed and high resolution characteristics. Fast and simple design of analog circuits using CAD tools, is highly sought after by integrated circuit designers. In this thesis, pipeline analog to digital converters is studied and a CAD tool is proposed for transistor level design and optimizations. The main advantage of this design in comparison with the previous works is that the yield and power consumption are considered as optimization factors. The module operates in three parts: optimization, simulation and decision. Simulation results approve the system level design and for a 10bit 40Ms/s analog to digital converter design, cadence simulation results show that with a 9.8bit ENOB, the converter consumes only 6.3 mW
Keywords:
Optimization ; Yeild ; Pipelines ; Design Optimization ; Analog to Digital Converter

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