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LER: Least-error-rate replacement algorithm for emerging STT-RAM caches

Hosseini Monazzah , A. M ; Sharif University of Technology | 2016

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  1. Type of Document: Article
  2. DOI: 10.1109/TDMR.2016.2562021
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2016
  4. Abstract:
  5. Spin-transfer-torque RAMs (STT-RAMs) are the most promising technology for replacing Static RAMs (SRAMs) in on-chip caches. One of the major problems in STT-RAMs is the high error rate due to stochastic switching in write operations. Cache replacement algorithms have a major role in the number of write operations into the caches. Due to this fact, it is necessary to redesign cache replacement algorithms to consider the new challenges of STT-RAM caches. This paper proposes a cache replacement algorithm, which is called least error rate (LER) , to reduce the error rate in L2 caches. The main idea is to place the incoming block in a line that incurs the minimum error rate in write operation. This is done by comparing the contents of the incoming block with lines in a cache set. Compared with Least Recently Used (LRU) algorithm, LER reduces the error rate by 2× with about 1.4% and 3.6% performance and dynamic energy consumption overheads, respectively. Moreover, LER imposes no area overhead to system
  6. Keywords:
  7. STT-RAM ; Cache memory ; Energy utilization ; Errors ; Stochastic systems ; Cache replacement algorithm ; Dynamic energy consumption ; Error rate ; Least recently used algorithms ; Replacement algorithm ; Spin transfer torque ; Stochastic switching ; Stt rams ; Algorithms
  8. Source: IEEE Transactions on Device and Materials Reliability ; Volume 16, Issue 2 , 2016 , Pages 220-226 ; 15304388 (ISSN)
  9. URL: http://ieeexplore.ieee.org/document/7464296