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LATED: lifetime-aware tag for enduring design

Ghaemi, S. G ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1109/EDCC.2015.31
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2015
  4. Abstract:
  5. Nowadays, leakage energy constitutes up to 80% of total cache energy consumption and tag array is responsible for a considerable fraction of static energy consumption. An approach to reduce static energy consumption is to replace SRAMs by STT-RAMs with near zero leakage power. However, a problem of an STT-RAM cell is its limited write endurance. In spite of previous studies which have targeted the data array, in this study STT-RAMs are used in the L1 tag array. To solve the write endurance problem, this paper proposes an STTRAM/SRAM tag architecture. Considering the spatial locality of memory references, the lower significant bitlines of the tag update more. The SRAM part handles the updates in the bit-lines which their lifetime is less than the desired lifetime. The proposed architecture is evaluated by the gem5 simulator running Mibench benchmark suits. The evaluation results recommend implementing less than 30% of bit-lines of the STT-RAM-based tag array by SRAMs for a 5-year lifetime. Moreover, the static energy consumption is reduced up to 82 % in comparison with SRAM tag array
  6. Keywords:
  7. Cache ; Endurance ; STT-RAM ; Tag array ; Durability ; Energy utilization ; Integrated circuit design ; Static random access storage ; Cache ; Cache energy consumption ; Evaluation results ; Lifetime ; Proposed architectures ; Spatial locality of memory references ; Stt rams ; Tag arrays ; Random access storage
  8. Source: Proceedings - 2015 11th European Dependable Computing Conference, EDCC 2015, 7 September 2015 through 11 September 2015 ; 2015 , Pages 97-107 ; 9781467392891 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/7371958/?arnumber=7371958&tag=1