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Low power encoding in NoCs based on coupling transition avoidance

Taassori, M ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/DSD.2009.207
  3. Abstract:
  4. Coupling capacitances between adjacent wires in on-chip interconnects significantly affect the amount of power consumption in Ultra-Deep-Submicron technologies. On the other hand, the propagation delay across global on chip interconnects has increasingly become a limiting factor in high-speed design. Crosstalk between adjacent links on the bus contributes a significant portion of this delay. Crosstalk noise also affects the integrity of signals. Decreasing the coupling transitions can improve the side effects of crosstalk noise. We propose an algorithm to minimize the coupling activity transition. We also introduce a new solution to fit the proposed algorithm for Network-on-Chip (NoC) architecture. The experimental results show that the proposed algorithm reduces the power consumption of NoCs up to 27% in an 8-bit bus. © 2009 IEEE
  5. Keywords:
  6. Low power encoding ; Coupling capacitance ; Coupling transition ; Crosstalk noise ; Deep sub-micron technology ; High speed designs ; Limiting factors ; Low power ; Network on chip ; Network-on-chip architectures ; New solutions ; On-chip interconnects ; Power consumption ; Propagation delays ; Side effect ; Algorithms ; Biological materials ; Capacitance ; Crosstalk ; Electric network topology ; Encoding (symbols) ; Microprocessor chips
  7. Source: 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009, 27 August 2009 through 29 August 2009 ; 2009 , Pages 247-254 ; 9780769537825 (ISBN)
  8. URL: http://ieeexplore.ieee.org/document/5350249