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Low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range

Movahedian Attar, H ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. DOI: 10.1007/s10470-009-9282-1
  3. Publisher: 2009
  4. Abstract:
  5. A new technique for improving the performance of low-voltage folding ADC's by extending the input range is presented. It is shown that by using both PMOS and NMOS differential pairs in the folding blocks, the overall input voltage range of the ADC can be increased to rail-to-rail. A novel self-adjustment method is also introduced to compensate for the different input-output characteristics of PMOS and NMOS differential pairs. A low voltage 8-bit 80 MSample/s folding/interpolating ADC is then designed and fabricated in a 0.18 μm CMOS process. Operating with a supply voltage as low as 1.2 V, measurements show an INL below ±0.55 LSB, SNDR of 43.5 dB at 80 MHz Sampling Frequency and power dissipation of only 30 mW. © 2009 Springer Science+Business Media, LLC
  6. Keywords:
  7. Analog-to-digital conversion ; CMOS processs ; Differential pairs ; Folding ; Folding block ; Input voltage ranges ; Input-output characteristics ; Low Power ; Low voltages ; Low-voltage ; Power dissipation ; Rail-to-rail ; Rail-to-rail input ; Sampling frequencies ; Self-adjustment ; Supply voltages ; Time varying systems ; Multicarrier modulation
  8. Source: Analog Integrated Circuits and Signal Processing ; Volume 61, Issue 2 , 2009 , Pages 181-189 ; 09251030 (ISSN)
  9. URL: https://link.springer.com/article/10.1007/s10470-009-9282-1