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Performance and power efficient on-chip communication using adaptive virtual point-to-point connections

Modarressi, M ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. DOI: 10.1109/NOCS.2009.5071468
  3. Publisher: 2009
  4. Abstract:
  5. In this paper, we propose a packet-switched network-on-chip (NoC) architecture which can provide a number of low-power, low-latency virtual point-to-point connections for communication flows. The work aims to improve the power and performance metrics of packet-switched NoC architectures and benefits from the power and resource utilization advantages of NoCs and superior communication performance of point-to-point dedicated links. The virtual point-to-point connections are set up by bypassing the entire router pipeline stages of the intermediate nodes. This work addresses constructing the virtual point-to-point connections at run-time using a light-weight setup network. It involves monitoring the NoC traffic in order to detect heavy communication flows and setting up a virtual point-to-point connection for them using a run-time circuit construction mechanism. The evaluation results show a significant reduction in power and latency over a traditional packet-switched NoC. © 2009 IEEE
  6. Keywords:
  7. Circuit construction ; Communication performance ; Evaluation results ; Intermediate node ; Light weight ; Low Power ; Low-latency ; NoC architectures ; On chip communication ; Packet switched network ; Packet-switched ; Performance metrics ; Power efficient ; Resource utilizations ; Router pipeline ; Runtimes ; Virtual points ; Biological materials ; Communication ; Electric network topology ; Microprocessor chips ; Packet networks ; Switching circuits ; Routers
  8. Source: 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009, San Diego, CA, 10 May 2009 through 13 May 2009 ; 2009 , Pages 203-212 ; 9781424441433 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/5071468