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The design of a low-power high-speed current comparator in 0.35-μm CMOS technology

Ziabakhsh, S ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. DOI: 10.1109/ISQED.2009.4810278
  3. Publisher: 2009
  4. Abstract:
  5. A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. It aimed for low power consumption and high speed designs compared with other high speed designs. The simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the average power consumption is 130 μW for 100 nA input current at supply voltage of 1.8 V using 0.35 micron CMOS technology. © 2009 IEEE
  6. Keywords:
  7. Average power ; Biasing methods ; CMOS technology ; Current comparator ; Current comparators ; High speed designs ; High-speed ; Input current ; Instantaneous power ; Low currents ; Low input impedance ; Low power ; Low-power consumption ; Positive feedback ; Propagation delay ; Propagation delays ; Simulation result ; Supply voltages ; CMOS integrated circuits ; Comparators (optical) ; Electric impedance ; Electric power utilization ; Feedback ; Power control ; Signal processing ; Design
  8. Source: Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009, 16 March 2009 through 18 March 2009, San Jose, CA ; 2009 , Pages 107-111 ; 9781424429530 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4810278