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Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

Fazeli, M ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. DOI: 10.1049/iet-cdt.2008.0099
  3. Publisher: 2009
  4. Abstract:
  5. Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50 less energy and occupies 42 less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90 of the injected SETs can be masked by the FERST latch if the delay size is properly selected. © The Institution of Engineering and Technology 2009
  6. Keywords:
  7. Deep sub micron technologies ; Delay elements ; Feature sizes ; Feedback lines ; Filter sets ; Low energies ; Seu tolerances ; Single event upsets ; Single events ; Single-event transients ; SPICE simulations ; Triple modular redundancies ; Digital integrated circuits ; Electric network analysis ; Fault tolerant computer systems ; Jitter ; Transients
  8. Source: IET Computers and Digital Techniques ; Volume 3, Issue 3 , 2009 , Pages 289-303 ; 17518601 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/4814319