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- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 50217 (05)
- University: Sharif University of Technology
- Department: Electrical Engineering
- Advisor(s): Sharifkhani, Mohammad
- Abstract:
- SRAM has a very wide application in different platforms including Cache Memory in Microcontrollers, etc. also SRAM is the first candidate for memory usage in every application needing High speed or static memory circuits. SRAM Cells are constructed by Minimum size transistors in each technology node and usually the newest technology nodes are used for building SRAM blocks for accommodating maximum number of SRAM Cells in a specific area. Going through smaller technology nodes, Leakage current and Process variations problem, creates serious difficulties in designing Low Power or High speed SRAM Memories and many academic and industrial works are done wishing for improvement in SRAM power consumption or operating speed. These problems are more viable while using SRAM Cells in subthreshold or near threshold voltages, because Ion to Ioff ratio is degraded exponentially by lowering supply voltage for SRAM Cells. This Thesis introduces a new method for decreasing the effect of Leakage Current of SRAM Cells in operating speed at near threshold voltage region and high temperature. For this purpose, transistors Leakage Current problem at operating voltage and other problems of new technologies including violent process variations in Fabrication process must be modeled and considered in design. The technique which is used in this thesis is SRAM column Leakage current compensation using decent Current mirrors and Dynamic calibration. The problems that appear in Calibration circuit timing and process variation must be considered in design process. Also, all of previously mentioned problems should be considered for designing Current mirrors with appropriate precision while injecting or sinking compensation current from SRAM columns. The effect of calibration time in SRAM speed and optimization of calibration time for attaining maximum speed in SRAM should be also considered. We have used TSMC 45nm technology file for simulation of the mentioned method and HSPICE and Spectre simulators are used for performing simulation on circuit. According to simulation results, Maximum SRAM Frequency has been increased by using proposed method and also Minimum working voltage has been decreased, making circuit suitable for near threshold and subthreshold working region
- Keywords:
- Static Random Access Memory (SRAM)Cell ; Process Variation ; Compensation ; Cache Memory ; Leakage Current
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