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Data Sharing Aware Scheduling for Reducing Memory Accesses in GPGPUs

Saber Latibari, Banafsheh | 2017

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 50439 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hesabi, Shahin
  7. Abstract:
  8. Access to global memory is one of the bottlenecks in performance and energy in GPUs. Graphical processors uses multi-thread in streaming multiprocessors to reduce memory access latency. However, due to the high number of concurrent memory requests, the memory bandwidth of low level memorties and the interconnection network are quickly saturated. Recent research suggests that adjacent thread blocks share a significant amount of data blocks. If the adjacent thread blocks are assigned to specific streaming multiprocessor, shared data block can be rused by these thread blocks. However the thread block scheduler assigns adjacent thread blocks to different streaming multiprocessors that increase load balancing. In this way, the use of data sharing between the thread blocks within each streaming multiprocessor becomes difficult. Also inside the streaming multi processors, there is the possibility of using data sharing between warps. In this thesis, we propuse a data sharing aware scheduler which uses data sharing in two level. The proposed scheduler first assign shared data blocks to the same stream multi processor, then in each stream multi processor the scheduler prioritize shared warps scheduling. which improves performance by 41.2% and power by 15.77% and energy consumption by 29.35% on average
  9. Keywords:
  10. Data Shairing ; General Purpose Graphic Processing Units (GPGPU) ; Hardware Schedular ; Threads ; Warp Scheduling ; Memory Access ; Thread Block

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