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Finite state machine based countermeasure for cryptographic algorithms

Attari, S ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/ISCISC.2017.8488336
  3. Abstract:
  4. In this work, we present a novel FPGA-based implementation of the AES algorithm which has a two-layered resistance against power analysis attacks. Our countermeasure is based on the concept of finite state machine equipped with a random number generator. Beyond masking the intermediate variables as the first layer of defense, we randomize the sequences of operations and add dummy computations as the second layer of defense. Therefore, the first order attack is prevented and the number of power traces needed for a successful second order attack is vastly increased and the correlation coefficient is decreased, as expected. © 2017 IEEE
  5. Keywords:
  6. Finite state machine ; Hiding ; Masking ; Side-channel-attack ; Chromium compounds ; Finite automata ; Network security ; Number theory ; Random number generation ; Speech intelligibility ; AES algorithms ; Correlation coefficient ; Cryptographic algorithms ; FPGA-based implementation ; Hiding ; Random number generators ; Second-order attacks ; Sequences of operations ; Side channel attack
  7. Source: 2017 14th International ISC (Iranian Society of Cryptology) Conference on Information Security and Cryptology, ISCISC 2017, 6 September 2017 through 7 September 2017 ; 2018 , Pages 58-63 ; 9781538665602 (ISBN)
  8. URL: https://ieeexplore.ieee.org/document/8488336