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High-Performance predictable NVM-based instruction memory for real-time embedded systems

Bazzaz, M ; Sharif University of Technology | 2018

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  1. Type of Document: Article
  2. DOI: 10.1109/TETC.2018.2858020
  3. Publisher: IEEE Computer Society , 2018
  4. Abstract:
  5. Worst case execution time and energy consumption are two of the most important design constraints of real-time embedded systems. Many recent studies have tried to improve the memory subsystem of embedded systems by using emerging non-volatile memories. However, accessing these memories imposes performance and energy overhead and using them as the code memory could increase the worst case execution time of the system. In this paper, a new code memory architecture for non-volatile memories is proposed which reduces the effective memory access latency by employing memory access interleaving technique. Unlike common instruction access latency improvement techniques such as prefetching and caching which usually increase the worst case execution time of the system, the proposed architecture is predictable. Furthermore, it improves both average case execution time and energy consumption of the system and requires no changes to the application code. The proposed architecture has been evaluated using different applications from MiBench and Malardalen benchmark suites and the results show that compared to previous studies, the proposed architecture can improve the memory energy consumption, the average case execution time, and the worst case execution time of the system by 73%, 61%, and 27% respectively. IEEE
  6. Keywords:
  7. Embedded systems ; Energy consumption ; Memory management ; Nonvolatile memory ; Real-time embedded system ; Real-time systems ; Worst case execution time analysis ; Benchmarking ; Codes (symbols) ; Energy utilization ; Interactive computer systems ; Memory architecture ; Nonvolatile storage ; Phase change materials ; Phase change memory ; Real time systems ; Non-volatile memory ; Random access memory ; Real-time embedded systems ; Worst-case execution time analysis
  8. Source: IEEE Transactions on Emerging Topics in Computing ; 2018 ; 21686750 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8423095