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A 5.3ps 8b Time to digital converter using a new gain-reconfigurable time amplifier

Molaei, H ; Sharif University of Technology | 2018

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSII.2018.2853187
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2018
  4. Abstract:
  5. Time amplifiers (TA) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18 μ m CMOS technology. Using a supply voltage of 1.2V, the proposed TDC consumes 1.1mW at 30MS/s throughput. IEEE
  6. Keywords:
  7. Re-Configurable Gain ; SR latch ; Time-to-digital converter ; Amplifiers (electronic) ; Light amplifiers ; NAND circuits ; Radiation detectors ; Signal processing ; Building blockes ; CMOS technology ; High resolution ; Low Power ; Metastabilities ; Supply voltages ; Time amplifier ; Time to digital converters ; Frequency converters
  8. Source: IEEE Transactions on Circuits and Systems II: Express Briefs ; 2018 ; 15497747 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8404116