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A resistive ram-based FPGA architecture equipped with efficient programming circuitry

Khaleghi, B ; Sharif University of Technology | 2018

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSI.2017.2778113
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2018
  4. Abstract:
  5. Despite the considerable effort has been put on the application of Non-Volatile Memories (NVMs) in Field-Programmable Gate Arrays FPGAs, previously suggested designs are not mature enough to substitute the state of-the-art SRAM-based counterparts mainly due to the inefficient building blocks and/or the overhead of programming structure which can impair their potential benefits. In this paper, we present a Resistive Random Access Memory RRAM-based FPGA architecture employing efficient Switch Box (SB) and Look-Up Table (LUT) designs with programming circuitry integrated in both SB and LUT designs that creates area and power efficient programmable components while precluding performance overhead to these blocks. In addition, we present an efficient scheme to load the configuration bitstream into the memory elements, which makes the configuration time comparable to that of SRAM-based FPGAs. Besides, we investigate the correct functionality and reliability of the programming structure subject to fluctuations in attributes of RRAM cells. Using Versatile Place and Route (VTR) tool with the obtained characteristics of the proposed blocks demonstrate that the average area and delay of the proposed FPGA architecture are 59.4% and 20.1% less than conventional SRAM-based FPGAs. Compared with a recent RRAM-based architecture, the proposed architecture improves the area and power by 49.7% and 33.8% while keeps the delay intact. © 2004-2012 IEEE
  6. Keywords:
  7. Emerging non-volatile memory ; Field-programmable gate arrays ; Programming circuitry ; Resistive fluctuation ; Electric resistance ; Logic gates ; Mathematical programming ; Memory architecture ; Phase change materials ; Phase change memory ; RRAM ; Static random access storage ; Table lookup ; Timing circuits ; Configuration bitstream ; Programmable components ; Programming structures ; Proposed architectures ; Random access memory ; Resistive random access memory ; Field programmable gate arrays (FPGA)
  8. Source: IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 65, Issue 7 , 2018 , Pages 2196-2209 ; 15498328 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8260547