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A low-power comparator-reduced flash ADC using dynamic comparators

Molaei, H ; Sharif University of Technology | 2018

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  1. Type of Document: Article
  2. DOI: 10.1109/ICECS.2017.8292010
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2018
  4. Abstract:
  5. This paper presents a new low-power reduced comparator flash ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce offset and kick-back noise effect of conventional dynamic comparators, a new comparator with a higher pre-amplifier gain along with the mathematical analysis is presented. The proposed 4bit ADC is simulated in 0.18um with 1.8-υ supply voltage. SNDR and SFDR of the ADC are 23dB and 26.5dB, respectively. The ADC consumes only 0.95mw at the sampling rate of 400MS/s. © 2017 IEEE
  6. Keywords:
  7. Analog-to-digital converter ; Delay derivation ; Dynamic comparator ; Low power ; Reference voltage implementation ; Analog to digital conversion ; Comparator circuits ; Analog to digital converters ; Dynamic comparators ; Reference voltages ; Comparators (optical)
  8. Source: 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, 5 December 2017 through 8 December 2017 ; Volume 2018-January , 2018 , Pages 5-8 ; 9781538619117 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/8292010