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Express read in MLC phase change memories

Jalili, M ; Sharif University of Technology | 2018

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  1. Type of Document: Article
  2. DOI: 10.1145/3177876
  3. Publisher: Association for Computing Machinery , 2018
  4. Abstract:
  5. In the era of big data, the capability of computer systems must be enhanced to support 2.5 quintillion byte/day data delivery. Among the components of a computer system, main memory has a great impact on overall system performance. DRAM technology has been used over the past four decades to build main memories. However, the scalability of DRAM technology has faced serious challenges. To keep pace with the ever-increasing demand for larger main memory, some new alternative technologies have been introduced. Phase change memory (PCM) is considered as one of such technologies for substituting DRAM. PCM offers some noteworthy properties such as low static power consumption, nonvolatility, and capability of storing more than one bit per cell (multilevel cell, or MLC). However, the short lifetime and long access latency of PCM (specifically MLC PCM) require feasible and efficient solutions. In this article, based on the observation that applications access a significant number of read-friendly data blocks, we propose Express Read to prevent the MLC PCM read circuit to spend unnecessary time sensing the cells of a memory block. A read-friendly data block (RFDB) is composed of only “11” and “00” bit pairs, and thus upon sensing the most significant bit of a cell, the read operation can be early terminated to reduce the MLC read time and power consumption. Moreover, we increase the number of RFDBs using two simple techniques to better exploit the benefits of Express Read. Results obtained from full-system simulation near 6% performance improvement and 21% energy gain, on average, over the baseline system. © 2018 ACM
  6. Keywords:
  7. Nonvolatile cache ; NVM ; STT-RAM ; Big data ; Cells ; Cytology ; Dynamic random access storage ; Electric power utilization ; Flash memory ; Random access storage ; Lifetime ; Non-volatile ; Stt rams ; Uniformity ; Wear leveling ; Phase change memory
  8. Source: ACM Transactions on Design Automation of Electronic Systems ; Volume 23, Issue 3 , February , 2018 ; 10844309 (ISSN)
  9. URL: https://dl.acm.org/citation.cfm?id=3177876