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REACT: Read/write error rate aware coding technique for emerging STT-MRAM caches

Aliagha, E ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1109/TMAG.2019.2905523
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2019
  4. Abstract:
  5. Spin-transfer torque magnetic RAMs (STT-MRAMs) are the most promising alternative for static random-access memories in large last-level on-chip caches due to their higher density and near-zero leakage power. However, the reliability of STT-MRAMs is threatened by high probability of read disturbance and write failure. Both read disturbance and write failure, which cause a soft error in the cache cells, have an asymmetric behavior. Read disturbance occurs only in STT-MRAM cells storing '1' value, and write failure error rate in a → 1 transition is much higher than that in a 1 → 0 transition. In this paper, we propose Read/write Error-rate Aware Coding Technique (REACT) to improve the reliability of the emerging STT-MRAM caches. REACT decreases the read disturbance and write failure rates by reducing the total number of '1's and 0 → 1 transitions on a cache block update. Our simulation results show that REACT reduces the probability of read disturbance and write failure up to 58% and 71%, respectively. These improvements are achieved by imposing negligible area, power, and performance overheads (less than 1%). © 1965-2012 IEEE
  6. Keywords:
  7. Data coding ; read disturbance ; spin-transfer torque magnetic ram (STT-MRAM) cache ; write failure ; Codes (symbols) ; Errors ; Failure analysis ; Magnetic leakage ; Magnetic recording ; Outages ; Radiation hardening ; Static random access storage ; Asymmetric behaviors ; Coding techniques ; High probability ; Magnetic rams ; Spin transfer torque ; Static random access memory ; MRAM devices
  8. Source: IEEE Transactions on Magnetics ; Volume 55, Issue 5 , 2019 ; 00189464 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8681736