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A 5.3-ps, 8-b time to digital converter using a new gain-reconfigurable time amplifier

Molaei, H ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSII.2018.2853187
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2019
  4. Abstract:
  5. Time amplifiers (TAs) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18- μm CMOS technology. Using a supply voltage of 1.2 V, the proposed TDC consumes 1.1 mW at 30 MS/s throughput. © 2004-2012 IEEE
  6. Keywords:
  7. Re-configurable gain ; SR latch ; Time-to-digital converter ; Amplifiers (electronic) ; Light amplifiers ; NAND circuits ; Radiation detectors ; Signal processing ; Building blockes ; CMOS technology ; High resolution ; Low power ; Metastabilities ; Supply voltages ; Time amplifier ; Time to digital converters ; Frequency converters
  8. Source: IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 66, Issue 3 , 2019 , Pages 352-356 ; 15497747 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8404116