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An efficient SRAM-Based reconfigurable architecture for embedded processors

Tamimi, S ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1109/TCAD.2018.2812118
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2019
  4. Abstract:
  5. Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, field-programmable gate arrays (FPGAs) are commonly used to implement either an entire embedded system or a hardware description language-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors in low-power embedded systems. In this paper, we present an efficient reconfigurable architecture to implement soft-core embedded processors in SRAM-based FPGAs by using characteristics such as low utilization and fragmented accessibility of comprising units. To this end, we integrate the low utilized functional units into efficiently designed look-up table (LUT)-based reconfigurable units (RUs). To further improve the efficiency of the proposed architecture, we used a set of efficient configurable hard logics that implement frequent Boolean functions while the other functions will still be employed by LUTs. We have evaluated effectiveness of the proposed architecture by implementing the Berkeley RISC-V processor and running MiBench benchmarks. We have also examined the applicability of the proposed architecture on an alternative open-source processor (i.e., LEON2) and a digital signal processing core. Experimental results show that the proposed architecture as compared to the conventional LUT-based soft-core processors improves area footprint, static power, energy consumption, and total execution time by 30.7%, 32.5%, 36.9%, and 6.3%, respectively. © 1982-2012 IEEE
  6. Keywords:
  7. Microprocessors ; Partial reconfiguration ; Power dissipation ; Reconfigurable logic ; Soft-core processors ; Computer hardware description languages ; Digital signal processors ; Electric power utilization ; Energy utilization ; Logic gates ; Program processors ; Reconfigurable architectures ; Safety engineering ; Switches ; Table lookup ; Digital signal processing (DSP) ; Field programmable gate array (FPGAs) ; Hardware description languages (HDL) ; High power consumption ; Low power embedded systems ; Power demands ; Proposed architectures ; Safety critical applications ; Embedded systems
  8. Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 38, Issue 3 , 2019 , Pages 466-479 ; 02780070 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8316989