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Design and Implementation of True Time Delay (TTD) Circuits in 0.18μm CMOS for Transceiver Module Application

Ghazizadeh, Mohammad Hossein | 2020

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 52988 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Medi, Ali
  7. Abstract:
  8. In order to improve the performance of radar systems, encouraging the movement towards multifunctional applications, wider frequency span is required to be considered for phased array systems constituting radars. The conventional approach of phase shifting is not applicable to wideband phased array system, and the need for phased array systems based on time delay is apparent. In active phased array systems where a transceiver module is placed before each radiating element, the task of controlling the delay and gain variation of each path is assigned to individual core chips residing in the transceiver modules. A typical core chip consists of several amplifying blocks along, with delay and gain control circuitry, all being integrated together. The main source of signal loss in the core chip is originated to the time delay blocks which are also known as true time delay blocks. In regard of general phase shifter blocks, these losses are higher which results in a lower performance for delay-based core chips in comparison to their phase shift counterparts. Therefore wideband radar systems based on true time delay would have inferior performance than narrow band radar systems which incorporate phase shifters. With the goal of improving the performance indexes of delay-based core chips, including gain, noise figure and linearity; achieving low loss true time delay blocks seems promising. Thus, as a research subject for doctorate dissertation, investigation and innovation of methods and techniques for designing low loss delay circuitry for wideband applications has been considered. Moreover a core chip based on true time delay having two RF paths for reception and transmission, with 6-bit time delay control and a maximum delay of 125 ps, 5-bit gain control with a resolution of 0.5 dB, a maximum gain of 10 dB, a noise figure of 9 dB and an input compression point of 0 dBm would be designed and implemented in 0.18μm CMOS intended to cover the wide bandwidth of 8 to 18 GHz. The propsed core chip which has higher limits imposed on its performance characteristics compared to trivial core chips; will be incorporating the novel approaches of lowering the loss associated with true time delay blocks. In this report the system-level design of the targeted core chip is addressed
  9. Keywords:
  10. Complementary Metal Oxide Semiconductor Technology (CMOS) ; System-Level Design ; Wideband Phased Array System ; True Time Delay Core Chips

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