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NoC design methodologies for heterogeneous architecture

Alhubail, L ; Sharif University of Technology | 2020

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  1. Type of Document: Article
  2. DOI: 10.1109/PDP50117.2020.00052
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2020
  4. Abstract:
  5. Fused CPU-GPU architectures that utilize the powerful features of both processors are common nowadays. Using homogeneous interconnect for such heterogeneous processors can result in performance degradation and power increase. This paper explores the optimization of heterogeneous NoC design to connect heterogeneous CPU-GPU architecture in terms of NoC performance and power. This involves solving four different NoC design sub-problems simultaneously; processing elements (PEs) mapping, buffer size and virtual channel assignments, and links' bandwidth determination. Heuristic-based optimization methods were proposed to obtain a near-optimal heterogeneous NoC design, and formal models were used to get a measure of the NoC performance and power of the evaluated design. The obtained optimal designs were validated using a full-system simulator. © 2020 IEEE
  6. Keywords:
  7. CPU-GPU ; Evolutionary algorithm ; Heterogeneous architecture ; Performance ; Power ; Graphics processing unit ; Heuristic methods ; Network architecture ; Network-on-chip ; Optimization ; Parallel processing systems ; CPU-GPU architectures ; Full system simulators ; Heterogeneous architectures ; Heterogeneous NoC ; Heterogeneous processors ; Optimization method ; Performance degradation ; Processing elements ; Integrated circuit design
  8. Source: Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020, 11 March 2020 through 13 March 2020 ; 2020 , Pages 299-306
  9. URL: https://ieeexplore.ieee.org/document/9092403