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Inter-line level schemes for handling hard errors in PCMs

Asadinia, M ; Sharif University of Technology | 2020

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  1. Type of Document: Article
  2. DOI: 10.1016/bs.adcom.2019.10.002
  3. Publisher: Academic Press Inc , 2020
  4. Abstract:
  5. To address the problem of fast degradation in PCM main memory systems in the presence of severe cell wear-out, this chapter introduces and evaluates some ways to deal with hard error issues in phase change memory. Our observation reveals when some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redirection or correction schemes to alleviate this problem, but all suffer from poor throughput or latency. In this chapter, we also propose On-demand page paired PCM (OD3P) memory system. Our technique mitigates the problem of fast failure of pages by redirecting them onto other healthy pages, leading to gradual memory capacity degradation. We then extend our proposed scheme at line-level, called line-level OD3P as a way to increase the durability of PCM pages by enabling line pairing within a page. Afterwards, we introduce our simulation environment and experimental results of our evaluations. © 2020 Elsevier Inc
  6. Keywords:
  7. Endurance ; Hard error ; Line-level pairing ; Multi-level cell PCM ; Page fault and page pairing ; Phase change memory (PCM) ; Wear-leveling
  8. Source: Advances in Computers ; Volume 118 , 2020 , Pages 49-78
  9. URL: https://www.sciencedirect.com/science/article/pii/S0065245819300555