Loading...

Integration of system-level IP cores in object-oriented design methodologies

Hashemi Namin, S ; Sharif University of Technology | 2008

495 Viewed
  1. Type of Document: Article
  2. DOI: 10.1007/978-3-540-89985-3_13
  3. Publisher: 2008
  4. Abstract:
  5. IP core reuse is popular for designing and implementing complex systems, because reuse of already provided blocks decreases design time and so diminishes productivity gap. Moreover, as system-level design methodologies and tools emerge for embedded system design, it is useful to have a shift from Register Transfer Level to system-level models for IP cores employed for implementation of hardware parts of the system. In this paper, we propose a C++ model for hardware IP cores that can be adopted as a standard for delivering IPs at a high level of abstraction, suitable for object-oriented system-level design methodologies. Next, we extend our system-level synthesizer in order to integrate IP cores automatically in a system architecture model generated by the synthesizer. Finally, we validate the extended synthesizer by designing and implementing systems with proposed C++ IP cores in our extended system-level design environment. © 2008 Springer-Verlag
  6. Keywords:
  7. Complex systems ; Design time ; Embedded system design ; Extended systems ; Hardware IP ; High level of abstraction ; IP core ; Object-oriented design ; Object-oriented system ; Register transfer level ; System architectures ; System level design ; System levels ; System-level models ; Computer science ; Design ; Embedded software ; Embedded systems ; Systems analysis ; Computer hardware
  8. Source: 13th International Computer Society of Iran Computer Conference on Advances in Computer Science and Engineering, CSICC 2008, Kish Island, 9 March 2008 through 11 March 2008 ; Volume 6 CCIS , 2008 , Pages 106-114 ; 18650929 (ISSN); 3540899847 (ISBN); 9783540899846 (ISBN)
  9. URL: https://link.springer.com/chapter/10.1007/978-3-540-89985-3_13