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A power efficient masking technique for design of robust embedded systems against SEUs and SETs

Fazeli, M ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1109/DFT.2008.33
  3. Publisher: 2008
  4. Abstract:
  5. In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (Single Event Transient and Upset Robust latch) is presented and evaluated. The SETUR is based on the use of a redundant feedback line and a CMOS delay element to tolerate the effect of the SETs occurring in the input line of the latch as well as SEUs occurring inside the latch. The experimental results show that the probability of an SET resulting in a soft error can be reduced up to 90% by choosing a proper delay value. The soft error rate of the SETUR due to SEUs occurring inside the latch is reduced by 95% while having lower area, power and performance overhead than the previously proposed latches. © 2008 IEEE
  6. Keywords:
  7. Delay elements ; Delay values ; Feedback line ; Masking technique ; Power efficient ; Single event transients ; Soft error ; Soft error rate ; Fault tolerance ; Fault tolerant computer systems ; Probability density function ; Quality assurance ; Transients ; Embedded systems
  8. Source: 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008, Boston, MA, 1 October 2008 through 3 October 2008 ; October , 2008 , Pages 193-201 ; 15505774 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/4641173