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A performance and functional assertion-based verification methodology at transaction-level

Hatefi Ardakani, H ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1109/ICM.2007.4497678
  3. Publisher: 2007
  4. Abstract:
  5. In this paper, we present an assertion-based verification methodology for system-level design. Transactionlevel concepts are integrated with an assertion language to introduce a useful, effective and familiar assertion description language. Our assertion verification language is capable of specifying system-level assertions for validating performance as well as functional properties. Proper-ties can be verified using offline simulation trace analysis. C++ trace checkers are automatically generated to validate particular simulation runs or to analyze their performance characteristic(s). Using a JPEG decoder as a case study, we demonstrate that the assertion-based verification is highly useful for both functional and performance system-level verification. © 2007 IEEE
  6. Keywords:
  7. Linguistics ; Microelectronics ; Assertion languages ; Assertion verifications ; Assertion-based verification ; Automatically generated ; Description languages ; Functional properties ; JPEG decoders ; Offline simulations ; Performance characteristics ; Performance systems ; System levels ; System-level design ; Trace checkers ; Transaction-level verification ; Trace analysis
  8. Source: 19th International Conference on Microelectronics, ICM, Cairo, 29 December 2007 through 31 December 2007 ; 2007 , Pages 133-136 ; 9781424418473 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4497678