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Evaluation of traffic pattern effect on power consumption in mesh and torus network-on-chips

Koohi, S ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1109/ISICIR.2007.4441911
  3. Publisher: 2007
  4. Abstract:
  5. Technology scaling increases clock rates and die sizes; therefore, power dissipation is predicted to soon become the key limiting factor on the performance of single-chip designs. NoC as an efficient and scalable on-chip communication architecture for SoC architectures, enables integration of a large number of computational and storage blocks on a single chip. Since different applications impose different traffic models to the network, in this paper we will analyze the power and energy consumption of the most popular traffic models, i.e., Uniform, Local, HotSpot and First Matrix Transpose, in two famous and well designed topologies, mesh and torus. We will also compare these topologies with considering two figures of merit, i.e. power consumption and power per throughput ratio and choose the best topology under different traffic models with respect to each of these figures of merit. © 2007 IEEE
  6. Keywords:
  7. Electric network topology ; Electric power utilization ; Integrated circuits ; Microprocessor chips ; Routers ; Topology ; Figures of merit ; Traffic modelling ; Computer networks
  8. Source: 2007 International Symposium on Integrated Circuits, ISIC, Singapore, 26 September 2007 through 28 September 2007 ; 2007 , Pages 512-515 ; 1424407974 (ISBN); 9781424407972 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4441911