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A low-power and SEU-tolerant switch architecture for network on chips

Patooghy, A ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1109/PRDC.2007.59
  3. Publisher: 2007
  4. Abstract:
  5. High reliability, high performance, low power consumption are the main objectives in the design of NoCs. These three design objectives are mostly conflicting and should be considered simultaneously in order to have an optimal design. This paper proposes a method based on duplicating the virtual channels of each NoC node as well as parity codes to prevent SEUs from producing erroneous data. The method is compared with two widely used SEU-tolerant methods i.e., the Switch to Switch and the End to End flow control methods, in terms of reliability, power consumption and performance. A flit level VHDL-based simulator and Synopsys Power Compiler tool have been used to extract experimental results. The simulation results show the same reliability for all three methods, while the proposed method shows the lowest power consumption and the highest performance almost in all traffic generation rates and all packet error rates. © 2007 IEEE
  6. Keywords:
  7. Electric network analysis ; Electric network topology ; Electric power utilization ; Error analysis ; Microprocessor chips ; Switching circuits ; Uranium powder metallurgy ; Dependable computing ; Design objectives ; End to end ; Flow control methods ; High-reliability ; International symposium ; Low powers ; Low-power consumption ; Network on chips ; NoC ; Optimal designs ; Pacific rim ; Packet error rates ; Parity codes ; Power consumption ; SEU-tolerance ; SEU-tolerant ; Simulation results ; Switch architectures ; Synopsys ; Traffic generation ; Virtual channels ; Power generation
  8. Source: 13th Pacific Rim International Symposium on Dependable Computing, PRDC 2007, Melbourne, VIC, 17 December 2007 through 19 December 2007 ; 2007 , Pages 264-267 ; 0769530540 (ISBN) ; 9780769530543 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4459669