Loading...

An empirical investigation of mesh and torus NoC topologies under different routing algorithms and traffic models

Mirza Aghatabar, M ; Sharif University of Technology | 2007

247 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/DSD.2007.4341445
  3. Publisher: 2007
  4. Abstract:
  5. NoC is an efficient on-chip communication architecture for SoC architectures. It enables integration of a large number of computational and storage blocks on a single chip. NoCs have tackled the SoCs disadvantages and are scalable. In this paper, we compare two popular NoC topologies, i.e., mesh and torus, in terms of different figures of merit e.g., latency, power consumption, and power/throughput ratio under different routing algorithms and two common traffic models, uniform and hotspot. To the best of our knowledge, this is the first effort in comparing mesh and torus topologies under different routing algorithms and traffic models with respect to their performance and power consumption. © 2007 IEEE
  6. Keywords:
  7. Architectural design ; Computer networks ; Electric network topology ; Electric power utilization ; Mathematical models ; Microprocessor chips ; Systems analysis ; Topology ; Hotspot ; Mesh ; Network-on-chip (NoC) ; Torus ; Uniform ; Routing algorithms
  8. Source: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007, Lubeck, 29 August 2007 through 31 August 2007 ; October , 2007 , Pages 19-26 ; 076952978X (ISBN); 9780769529783 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4341445