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A power-efficient clock and data recovery circuit in 0.18 μm CMOS technology for multi-channel short-haul optical data communication

Tajalli, A ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1109/JSSC.2007.905234
  3. Publisher: 2007
  4. Abstract:
  5. This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 μm CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of 0.045 mm2 /channel, with the total aggregate data bit rate of 20 Gb/s. The measured FTOL is ±3.5% and no error was detected for a 231-1 pseudo-random bit stream (PRBS) input data for 30 minutes, meaning that the bit error rate (BER) is smaller than 10-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning range and compensated loop gain has been introduced to tune the center frequency of all CDR channels to the desired value. © 2007 IEEE
  6. Keywords:
  7. Bit error rate ; CMOS integrated circuits ; Data communication systems ; Error detection ; Jitter ; Phase locked loops ; Tuning ; Clock and data recovery circuit ; Frequency tolerance (FTOL) ; Gated-oscillator-based clock and data recovery circuits (GO CDRs) ; Jitter tolerance (JTOL) ; Pseudo-random bit stream (PRBS) input data ; Optical data processing
  8. Source: IEEE Journal of Solid-State Circuits ; Volume 42, Issue 10 , 2007 , Pages 2235-2244 ; 00189200 (ISSN)
  9. URL: https://ieeexplore.ieee.org.com/document/4317714