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Design of a Low-IF Phased-Array Receiver for 5G Applications

Ebrahimi Maroufi, Mojtaba | 2021

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 54163 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Fakharzadeh, Mohammad
  7. Abstract:
  8. The most important feature of the fifth generation of mobile telecommunications is the increase of information transfer rate and together with it the increase of the capacity of telecommunication channels in comparison with the previous generation. One solution is to increase the frequency toward millimeter-wave frequencies. Currently, the most suitable option for the millimeter-wave frequency band is the 28 GHz band, which has received a lot of attention due to its availability and the possibility of implementing cheap integrated circuits using CMOS technology in this band. In addition to the features that this frequency band has; This band has limitations such as high emission losses and on the other hand low transmission power due to the current limitations of the utilized technology. In the current study, we have used a phased-array system to overcome the challenges. A phased-array system consists of several transmitter / receiver units in order to improve the sensitivity and signal to noise ratio by changing the phase of the input signal on the receiver side and on the other hand on the transmitter side by using multiple antennas so as a result, the transmitted signal strength increases. To implement the receiver of a phased array system, we need a suitable front-end to receive and change the phase of the input signal and mixer and to reduce the input frequency for detection.Low-IF architecture, despite the problems such as LO leakage , DC offset, more flicker noise, etc., compared to others , has the advantage of less external component and less power loss, and as a result , this architecture has been used widely in the literature. In this thesis, we designed a phased-array receiver that includes low-noise amplifier and phaseshifter with a mixer in the 65nm-LP CMOS technology in the frequency band from 26 to 30 GHz. The low-noise amplifier is designed using common-source topology with a transformerbased input technique in order to reduce the size of the chip. A vector sum phase shifter is then designed to achieve 360 degree phase shifting range. The results of simulating the system shows a maximum of 26 dB gain and a minimum of 3.2 dB noise figure in the desired band-width. RMS gain and phase error are 0.17dB and 2.1 degree, respectively. Power consumption of the system is 116.8 mW
  9. Keywords:
  10. Receivers ; Mixer ; Phased Array ; Fifth Generation of Mobile Networks ; Low Noise Amplifier (LNA) ; Phase Shifter Circuit ; Front-End

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