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A 1/4 rate linear phase detector for PLL-based CDR circuits

Saffari, M ; Sharif University of Technology | 2006

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  1. Type of Document: Article
  2. DOI: 10.1109/ISCAS.2006.1693326
  3. Publisher: 2006
  4. Abstract:
  5. In this paper, a new 1/4 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits will be suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18μm CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply. © 2006 IEEE
  6. Keywords:
  7. Clock and data recovery (CDR) circuits ; Duty cycle ; Phase detector (PD) structure ; CMOS integrated circuits ; Electric network topology ; Phase locked loops ; Linear integrated circuits
  8. Source: ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 21 May 2006 through 24 May 2006 ; 2006 , Pages 3281-3284 ; 02714310 (ISSN); 0780393902 (ISBN); 9780780393905 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1693326