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A novel three-phase magnitude-phase-locked loop system

Karimi Ghartemani, M ; Sharif University of Technology | 2006

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSI.2006.879057
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2006
  4. Abstract:
  5. A novel three-phase magnitude-phase-locked-loop system (3MPLL) for use in the general area of three-phase (power, energy and power electronic) systems is introduced. The proposed 3MPLL suppresses the noise and distortion from the input signal, mitigates the unbalance, and synthesizes the instantaneous positive-sequence component of the input signal; thus it operates as a nonlinear adaptive notch (or band-pass) filter. The 3MPLL also adaptively tracks and estimates the magnitude, phase angle, and frequency of the input signal; thus, its operation as a nonlinear state estimator. Characteristics of the 3MPLL including its mathematical equations as well as steady-state and dynamic responses are discussed in this paper. Comparisons are made between the proposed 3MPLL and conventional single-phase PLL (1PLL) and three-phase PLL (3PLL) systems. Advantages of the proposed system over the conventional methods and systems are also discussed. Structural simplicity and robustness of the 3MPLL system are its further features which make it desirable. In addition to the conventional applications of the 3PLL in the general area of power systems, the proposed 3MPLL can also be used for other applications which require smooth and adaptive synthesis of the instantaneous symmetrical components. Particularly, the 3MPLL can be used as a three-phase nonlinear anti-aliasing filter with no phase-shift and no amplitude bias. Three unique features of such a filter are frequency adaptivity, unbalance mitigation, and structural simplicity/ robustness. © 2006 IEEE
  6. Keywords:
  7. Adaptive filtering ; Interference suppression ; Notch filters ; Phase shift ; Synchronization ; Adaptive notch filter ; Amplitude bias ; Anti-aliasing filter ; Frequency estimation ; Three-phase phase-locked loop ; Phase locked loops
  8. Source: IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 53, Issue 8 , 2006 , Pages 1792-1802 ; 10577122 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/1673648