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Efficient Routing Architectures for Reconfigurable Devices

Seifoori, Zeinab | 2021

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 54713 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Asadi, Hossein
  7. Abstract:
  8. Due to reduced Non-Recurring Engineering (NRE) costs, shorter time to market, design flexibility, and reprogramming capability of Field-Programmable Gate Arrays (FPGAs) as compared to Application-Specific Integrated Circuits (ASICs), FPGAs has been raised as a suitable substrate for implementation of digital systems. However, the high flexibility of reconfigurable devices leads to great power consumption, chip area, and reliability difference between ASICs and FPGAs. In addition, with the advent of multi-tenant FPGAs in cloud computing environments, it has been shown that crosstalk side-channel attack, which can be used by a malicious IP to leak valuable information, has become an urgent reliability concern in FPGA designs. Since routing resources contribute to more than half of total chip resources, reducing the power consumption and improving the reliability of routing resources can effectively help to improve power consumption, reliability, performance, and area of the total chip.The main aim of this thesis is to suggest architectures to enhance the efficiency of routing architecture of reconfigurable devices in the dark silicon era. In the first proposed architecture, the presented power gating architectures with different granularities for powering off unused configuration bits and routing resources can reduce the static power consumption up to 75%. In addition, by decreasing the number of susceptible configuration bits to soft error by 61.82% in the aforementioned architecture, the error rate is reduced. By improving the efficiency of the power gating regions in the second proposed architecture through employing the machine learning approaches we achieve (on average) almost 1.4x higher savings in the static power consumption of the FPGA routing resources at lower area overhead than the most efficient heuristic published so far. In addition, by improving the clustering metric and enhancing the routing algorithm to take advantage of power gating opportunities in the third proposed architecture, we achieve an improvement of about 70%, on average, in reducing the FPGA static power consumption over the best power-gating approaches proposed in the previous studies. Investigating the power consumption of various routing resources reveals that changing the signals probabilities can reduce the static power consumption. Hence, the fourth proposed architecture decreases the static power consumption by increasing the probability of logic signals with less power consumption as well as amending the buffer sizing. The fifth proposed in this thesis mitigates the aging effect in FPGA through cross-layer design techniques spanning from FPGA fabrication (i.e. pre-silicon optimization) to routing algorithms (i.e. post-silicon optimization). Our last proposed architecture improves the routing algorithm to prevent the crosstalk side-channel attack
  9. Keywords:
  10. Performance ; Power Consumption ; Cross Talk ; Dark Silicon ; Aging ; Reconfigurable Devices

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