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Duty-cycle controller for low-jitter frequency-doubling DLL

Tajalli, A ; Sharif University of Technology | 2005

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  1. Type of Document: Article
  2. DOI: 10.1049/ip-cds:20045151
  3. Publisher: 2005
  4. Abstract:
  5. This article introduces a novel duty-cycle control circuit (DCC) preceding a delay-locked loop (DLL)-based clock frequency multiplier preventing the output duty-cycle over process, supply voltage and temperature (PVT) variations. However, the proposed DCC eliminates the effect of input duty-cycle variation and, hence, decreases the sensitivity to the input jitter and distortion. The circuit realisation in 0.5-μm CMOS technology shows that the duty-cycle variation at the output clock is less than 2.7%, while driving the digital section of a CODEC chip and also test pads. The analysis, confirmed by measurements, shows a stable and accurate response for the proposed clock generation unit (CGU). © IEE, 2005
  6. Keywords:
  7. Clock generation unit (CGU) ; Delay-locked loop (DLL) ; Duty-cycle control circuit (DCC) ; Control equipment ; Electric potential ; Jitter ; Microprocessor chips ; Frequency multiplying circuits
  8. Source: IEE Proceedings: Circuits, Devices and Systems ; Volume 152, Issue 5 , 2005 , Pages 411-416 ; 13502409 (ISSN)
  9. URL: https://digital-library.theiet.org/content/journals/10.1049/ip-cds_20045151