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Design of a Strong Delay-based PUF for FPGA 6 Series Based Systems

Babaei, Ehsan | 2021

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 55276 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Haj Sadeghi, Khosro
  7. Abstract:
  8. There are three types of Slices in an FPGA, and based on the functionality of these slices, SliceM has the most features especially for designs based on shift registers, adders, and ROMs, and from all of the slices, 25% of them are SliceM. Among the earlier designs that are FPGA-based, Anderson PUF is that is classified as a weak delay-based PUF. In Anderson’s design there always should be atleast two SliceMs that their LUTs are configured as shift registers, the Andersons PUF in some FPGA Architecture especially Series 7 FPGAs, consumes two SliceMs and two other SliceLs, so practically we are using four of our precious slices. Rather than these, in series 6 FPGAs, the design should change for the delay extraction circuit and the register is consuming SliceX and SliceLs in addition to two SliceMs. In addition to these, in Anderson’s Design, it is been noted that for creating a Strong PUF using this weak PUF, we need to put together a large number of these PUFs and use a multiplexer as a backend and use the select pins as a challenge which this will end up using too many resources. Based on the functionality of SliceMs and the noted problems, in this research by changing our viewpoint about Anderson’s architecture and its idea of glitch-based design, we attempt to design a PUF that is completely flexible in the point of the type of slices to use and it is not dependent to FPGA Architecture. We have tried that our PUF can choose between SliceL or SliceM, this way when we need more SliceMs, we can use SliceL in the PUF instead. We have implemented the design on Spartan 6 Xilinx FPGA that has been assembled on Digilent boards and for optimization purposes, we used Xilinx ISE tools like PlanAhead, FPGA Editor and also we used Xilinx Constraint with VHDL for a better place and route for our design. In our implementation, we achieved 0.5133 of uniqueness which is so close to the ideal value of 0.5, and it is also closed to Anderson’s PUF and its family of designs. For the uniqueness, the average value was 0.5000 which is equal to the ideal value. In this implementation we will see that these results are so dependent on the placing of the circuit, so with the use of good placing, we can achieve results even equal to the ideal values.
  9. Keywords:
  10. Field Programmable Gate Array (FPGA) ; Very Highspeed Integrated Circuits Hardware Description Language (VHDL) ; Physical Unclonable Function (PUF) ; Xilinx Constraint ; Internet of Things ; Cryptography

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