Loading...

Error detection enhancement in COTS superscalar processors with event monitoring features

Rajabzadeh, A ; Sharif University of Technology | 2004

190 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/PRDC.2004.1276552
  3. Publisher: 2004
  4. Abstract:
  5. Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This paper presents an error detection scheme called Committed Instructions Counting (CIC) to increase error detection in such systems. The scheme uses internal Performance Monitoring features and an external watchdog processor (WDP). The Performance Monitoring features enable counting the number of committed instructions in a program. The scheme is experimentally evaluated on a 32-bit Pentium® processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into the Pentium® processor. The results show that the error detection coverage varies between to 90.92% and 98.41%, for different workloads
  6. Keywords:
  7. Event detection ; Computer industry ; Embedded computing ; Pins ; Runtime ; Computerized monitoring ; Condition monitoring ; Error correction ; Pipelines ; Computer errors
  8. Source: Proceedings - 10th IEEE Pacific Rim International Symposium on Dependable Computing, Papeete Tahiti, 3 March 2004 through 5 March 2004 ; 2004 , Pages 49-54 ; 0769520766 (ISBN); 9780769520766 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1276552