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A 1.8-V high-speed 13-bit pipelined analog to digital converter for digital IF applications

Aslanzadeh, H. A ; Sharif University of Technology | 2003

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  1. Type of Document: Article
  2. Publisher: 2003
  3. Abstract:
  4. A 1.8-v 13-bit 25MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.18um CMOS technology. The proposed new high speed low power class AB opamp makes it possible to achieve requirements of 13-bit resolution and settling in 12ns within 0.01% accuracy. An optimum architecture for noise and power consideration is also selected to reduce power. Total Power dissipation is about 82 mw from a single 1.8 v supply, where INL and DNL are 0.7 LSB and 0.6 LSB respectively. SNDR of 75.5 dB is achieved
  5. Keywords:
  6. Analog-digital conversion ; Power dissipation ; Noise reduction ; Capacitance ; Base stations ; Wideband ; CMOS technology ; Capacitors ; Personal communication networks
  7. Source: Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, Bangkok, 25 May 2003 through 28 May 2003 ; Volume 1 , 2003 , Pages I885-I888 ; 02714310 (ISSN)
  8. URL: https://ieeexplore.ieee.org/document/1205706