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A low power 25 MS/S 12-bit pipelined analog to digital converter for wireless applications

Aslanzadeh, H. A ; Sharif University of Technology | 2003

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  1. Type of Document: Article
  2. DOI: 10.1109/SSMSD.2003.1190393
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2003
  4. Abstract:
  5. A 12 bit 25 MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.35 μm CMOS technology. The proposed new high speed class AB opamp makes it possible to achieve requirements of 12 bit resolution and settling in 20 ns within 0.05% accuracy. However, pipeline ADCs are tolerant to comparator's offset, but using dynamic comparators, power dissipation can be reduced. So a dynamic comparator is designed which is more power efficient. Total power dissipation is about 76 mW from a single 3 V supply, where INL and DNL are 0.8 LSB and 0.6 LSB respectively. A SNDR of 70.1 dB is achieved. © 2003 IEEE
  6. Keywords:
  7. Analog-digital conversion ; Capacitance ; Capacitors ; Circuit noise ; CMOS technology ; Error correction ; Operational amplifiers ; Pipelines ; Power dissipation ; Sampling methods
  8. Source: 2003 Southwest Symposium on Mixed-Signal Design, SSMSD 2003, 23 February 2003 through 25 February 2003 ; 2003 , Pages 38-42 ; 0780377788 (ISBN); 9780780377783 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1190393