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Low Voltage Oscillator Design with the Lowest Reported Phase Noise in the 1/F3 Region at 3.6 GHzTitle

Askarzade Torghabe, Reyhaneh | 2023

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 56353 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Fotowat Ahmady, Ali; Akbar, Fatemeh
  7. Abstract:
  8. Oscillators are an important building block in the design of synthesizers for RF system applications. State-of-the-art operation defines that an oscillator should have the best spectral purity while consuming a low amount of power. In recent years, several methods have been presented for reducing phase noise separately in the 1/f2 and 1/f3 regions. As CMOS technology advances, the amount of power supplies decreases, which worsens the inherent flicker noise. In this thesis, it has been tried, while investigating the existing methods in the phase noise in this region, it presents the proposed oscillator which is based on a three-coupled transformer. This voltage bias oscillator operates at a frequency of 3.6 GHz. One of the important and key factors in determining the phase noise in the 1/f3 region is the high ratio of non-main components of the current to its main component. By using the concept of source degeneration, we have controlled the effect of this factor to a significant amount with a new method. In this design, the methods of source degeneration, harmonic adjustment, and passive gain are used to reduce the 1/f noise conversion power and improve the impact damage performance and thus the noise. According to the simulation results, the phase noise is -91.94 dBC/Hz at 10 kHz offset, and the figure of merit (FoM) is 196.2 dB. This oscillator consumes 4.7 mW of power from a 0.4 V power supply
  9. Keywords:
  10. Impulse Sensitivity Function (ISF) ; Flicker Noise ; Three Coupled Transformer ; Ultra Low Phase Noise ; Voltage Biased Oscillator ; Complementary Metal Oxide Semiconductor Technology (CMOS)

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